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FWBX3-PCIE1XE121

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FWBX3-PCIE1XE121

  • 所屬分類：映奧IOI

  • 型號：IOI映奧1394采集卡FWBX3-PCIE1XE121
  • 點擊次數：
  • 發(fā)布日期：2023/06/10
  • 在線詢價
詳細介紹

 映奧IOI采集卡

FWBX3-PCIE1XE121價格

Products

Host Adapters

FWBX3-PCIE1XE121 [Phased out]

Triple OHCI 3-port (1-port x 3) IEEE 1394b (FireWire 800) to PCI Express x1 Gen 2 Host Card

Highlights

· Host Bus: 1-lane 2.5 or 5.0 Gb/s PCI Express

· Triple OHCI 1.2 Compliant IEEE 1394b host controllers

· Designed with Late VG Protection

· Three external Bilingual IEEE Std 1394b-2002 Cable Ports

o Supports Bilingual Plug port with Jackscrew Type 1394b Cable

 

Introduction

The FWBX3-PCIE1XE121 is a Triple OHCI FireWire 800 (IEEE 1394b) to PCI Express x1 Gen 2 Host Adapter.

FWBX3-PCIE1XE121 is designed with two key components.

· 4-Lane, 4-Port PCI Express Switch.

· OHCI 1.2 Compliant IEEE 1394b Single Chip Host Controller.

Utilizing the standard PCI Express Switch, the 4-Lane/4-Port PCI Express Switch provides the most efficient fan-out solution for integrating three OHCI 1.2 Compliant IEEE 1394b (FireWire 800) to PCI Express Single Chip Host controllers into a small board design. Each OHCI 1.2 Compliant IEEE 1394b to PCI Express Single Chip Host controller takes advantages of 5 Gbps burst rate of 1-lane PCI Express bus in both directions and is fully compliant with PCI Express Base specification r2.1. This solution provides full PCI Express and IEEE 1394b (FireWire 800) functionality and performance.

 

Technical Specifications

PCI Express:· Standards complianto PCI Express Base Specification, Revision 2.1o Backward-compatible with the PCI Express Base Specification, Revision 1.1 (PCI Express Base r1.1) and PCI Express Base Specification, Revision 1.0a (PCI Express Base r1.0a)o PCI Bus Power Management Interface Specification, Revision 1.2 (PCI Power Mgmt. r1.2)o Microsoft Windows 7?-complianto Dynamic Link speed (2.5 or 5.0 GT/s) negotiationo Dynamic Link width negotiation· High Performanceo Non-Blocking Internal architectureo Full line rate on all Portso Cut-Thru packet latency of less than 250 ns between symmetric (x1 to x1)o Maximum Payload Size – 256 bytes· PCI Express Power Managemento Conventional PCI-compatible Link Power Management states – L0, L0s, L1, and L2/L3 Readyo Conventional PCI-compatible Device Power Management states –D0, D1, D2, and D3hoto Active State Power Management (ASPM)· Quality of Service (QoS) supporto All Ports support one, full-featured Virtual Channel (VC0)o All Ports support eight Traffic Classes (TC[7:0]) mapping, independently of the other Portso Weighted Round-Robin (WRR) Port arbitrationOHCI (Open Host Controller Interface)· Enhanced with the OHCI 1.2 draft specification for 1394b-2002 PHY full operational compliance.· OHCI 1.0 backwards compatible. Configurable via EEPROM to operate in either OHCI 1.0 or OHCI 1.1 mode.· 8 Kbyte isochronous transmit FIFO.· 4 Kbyte asynchronous transmit FIFO.· 8 Kbyte isochronous receive FIFO.· 8 Kbyte asynchronous receive FIFO.· Dedicated asynchronous and isochronous descriptor-based DMA engines.· Eight isochronous transmit contexts.· Eight isochronous receive contexts.· Supports parallel processing of incoming physical read and write requests.· Supports up to 48-bit addressing per OHCI specifica-tion for the physical DMA transfers.1394b-2002 Link· Support for calculation and checking of the cyclic redundancy check (CRC) on outgoing and incoming packets· Support for decoding the destination ID of incoming 1394 packets to determine if an acknowledge is needed.· Cycle master and isochronous resource manager capability· Support for 1394a-2000 and 1394b acceleration features1394b-2002 PHY· IEEE 1394b-2002 compliant ports supporting 1394b speeds of 800 Mb/s and 400 Mb/s while maintaining backward compatibility to IEEE 1394a-2000 speeds of 100 Mb/s, 200 Mb/s, and 400 Mb/s over 4.5 m copper.· Full support for IEEE 1394a-2000 and 1394-1995 standard provisions for high-performance serial bus.· Registers to indicate power class modes.· Extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders.· While unpowered and connected to the bus, the device does not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port.· No need for an external filter capacitor for PLL.· Link-on as a part of the internal PHY core-link interface.· Arbitrated short bus reset.· Ack-accelerated arbitration and fly-by concatenation.· Connection debounce.· Multispeed packet concatenation.· PHY pinging and remote PHY access packets.· Port disable/suspend/resume.· PHY-link interface initialization and reset.· Support for the 1394a-2000 register set.· Fully interoperable with FireWire? and i.LINK? implementation of IEEE 1394-1995.· Cable power fail interrupt reported when voltage at TPCPS pin falls below 7.5 V.· Separate cable bias and driver termination voltage supply for each port provided.Number of Ports:· Three External Bilingual ports with Screw Holes for thumbscrew locking Type 1394b CableBus Power Connector:· Big IDE 4-pin DC Power Connector or SATA 15-pin Power Connector

 

 

Operating System Requirements

· Windows 2000/XP/7/8/8.1 and Windows Server 2003

· Mac OS 10.4.8 or later

· Linux 2.6.X

 

Physical Dimensions

· 98(H)x113(L)mm

· NW: 73.3g

 

Certifications

· CE Test: Pass

· FCC Test : Pass

· VCCI Test: Pass

原裝全新臺產IOI映奧1394采集卡FWBX3-PCIE1XE121工業(yè)相機3口

原裝全新臺產IOI映奧1394采集卡FWBX3-PCIE1XE121工業(yè)相機3口

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